Modern integrated electronic circuits are routinely fabricated by means of complex and extensive manufacturing processes. Over recent years, the semiconductor industry has established very sophisticated and reliable manufacturing processes, the most prominent member thereof being the so-called CMOS process. In such a process, which usually comprises hundreds of single process stages, highly integrated electronic devices, such as microprocessors or electronic data memory devices, are formed on a semiconductor substrate.
Via an elaborate sequence of deposition, etching, lithographic, and relating techniques, a plurality of electronic entities, such as resistors, capacitors or transistors, are structured and interconnected on the semiconductor substrate. Nowadays, often the integration chip of as many electronic entities as possible on a single substrate determines the overall device performance, and, eventually, the economic success of an integrated circuit. Therefore, the reduction of the minimum feature size of said electronic elements is subject to intense industrial and scientific research and development.
As far as the device design and layout are concerned, increasing the integration of electronic elements on a substrate often translates to increasing the capacitance of capacitor elements of the integrated circuit. The main factors of improvement of capacitor elements include the formation of highly conductive layers as capacitor electrodes, alongside the adoption of materials that possess a high dielectric constant, such as the so-called high-k-materials. In the state of the art, highly conductive layers are deposited on dielectrics, which include alumina, silica, and related materials, whereas metals and metal composites, such as titanium-nitride and tantalum-nitride, find broad application as base materials for the highly conductive layers. Since in the field of integrated circuit manufacturing the physics and technology of silicon is most advanced, mainly poly-crystalline silicon is used for wiring and establishing electric contact to electrode elements, such as the capacitor electrodes. Therefore, usually a poly-crystalline silicon layer is deposited on top of the highly conductive layers.
As the direct deposition of poly-crystalline silicon is technologically inexpedient, state of the art manufacturing processes firstly deposit a layer of amorphous silicon, which is subsequently rendered poly-crystalline during a heating process. This phase change of the silicon is highly sensitive to the physical structure of the material which the silicon has been deposited. It has been shown that the crystallization of silicon to a poly-crystalline state on top of common highly conductive materials results in undesired stress, and, as a consequence, to substrate deformation. Latter substrate deformation, even to a minimal extent, cause severe problems during device manufacturing, since subsequent process stages have to be aligned to each other with a high grade of accuracy, which is made impossible by a deformed substrate.
For a further increase of the integration of electronic circuits and to maximize their overall device performance, the appropriate design measures must be implemented, while maintaining a reliable and efficient manufacturing process. Consequently, there is a need for improved measures for reducing the minimum feature size.